Neil P Turley
neilpturley@gmail.com
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(801) 854-8659
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South Jordan, Utah, US
Github
EXPERIENCE
Copia Automation
2021-02 — Present
Staff Engineer
2026-08 — Present
Engineering Manager
2022-10 — 2026-08
Software Engineer
2021-02 — 2022-10
Joined pre-revenue as the 4th employee; company has since grown past $10M ARR
Led the team that delivered rendering for 15+ graphical IEC languages
Implemented conversion and initial rendering for Siemens TIA Portal and Codesys
Reverse engineered three proprietary binary project file formats
Launched the initial Copia Desktop product
Managed the source control team of up to 6 engineers
Founded the company-wide technical architecture guild
Created the team's strategy for AI-assisted development
Led research spikes on high-risk projects and guided the team through two reorgs
Partnered with product managers to plan the product roadmap
Helped found the core applications team and onboarded its new members
Ran standups, retros, sprints, engineering meetings, on-call, and technical interviews
McCoy Global Inc - Lead Software Engineer
2019-11 — 2021-02
Maintained embedded microcontroller firmware (C)
Developed Data Acquisition/Reporting Software for Pipe Drilling Sensors (LabVIEW)
Managed AWS resources and build pipelines as code (Terraform, CloudFormation)
Implemented HTTP API endpoints that accessed database (C#, DynamoDB, AWS)
National Instruments, RIO Software - Staff Software Engineer
2014-01 — 2019-11
Wrote FPGA System Integration for Five RIO Product Lines (LabVIEW, VHDL)
Designed and Implemented a High Speed Data Transfer API (LabVIEW, VHDL, C++)
Ported LabVIEW FPGA RIO Driver to Zynq Platform (C++)
Proposed and Developed Hardware Anti-Cloning Mechanisms (VHDL, C++)
BYU Nuclear Physics Research Group - Lab Assistant
2010-10 — 2013-06
Writing Data Acquisition Software (C#, C)
Designing Digital Circuits and Layout (Mentor Graphics)
EDUCATION
Brigham Young University
2008 — 2014
Bachelor - Computer Engineering
PROJECTS
Latchup 2018: Netlistsvg
(https://github.com/nturley/netlistsvg)
Presented schematic visualization software; GitHub repo has 840+ stars
NIWeek 2017: Host Memory Buffer
Introduced a low-latency DMA interface for optimizing control loop determinism